What Is HyperCore Writer?

HyperCore Writer, also known as CoreWriter, is a system smart contract on HyperEVM at the fixed address 0x3333333333333333333333333333333333333333. It is the sole mechanism for HyperEVM smart contracts to write state changes to HyperCore, the native trading engine of the Hyperliquid layer 1.

CoreWriter exposes a single function sendRawAction(bytes) that accepts encoded action payloads. Each action is identified by an action ID:

  • Action 2 (vaultTransfer) — deposit or withdraw from a HyperCore native vault

  • Action 6 (spotSend) — bridge tokens from HyperCore back to HyperEVM (withdrawal to EVM)

  • Action 7 (transferUsdClass) — move USDC between spot and perpetual accounts on HyperCore

Other action IDs exist for placing limit orders, staking, and cancellations, but are typically restricted by vault guard contracts.

Asynchronous, non-atomic execution

CoreWriter actions are queued, not executed atomically. When sendRawAction() succeeds on HyperEVM, it only means the action entered the queue. HyperCore validators process the queue with a few seconds’ delay. An action can succeed on EVM but silently fail on HyperCore, with no revert propagation. This requires careful verification of HyperCore state via precompile reads in subsequent blocks.

When an EVM block finishes execution, all queued CoreWriter actions are processed sequentially on HyperCore (~47k gas per action) — implicit batching at the block level.

Guard integration

In the Trading Strategy Protocol vault architecture, a TradingStrategyModuleV0 guard contract whitelists specific CoreWriter action IDs and target vault addresses. The guard ensures that only authorised vault deposits/withdrawals, USDC class transfers, and spot sends to approved receivers can be executed through the Safe multisig. All other CoreWriter actions (limit orders, staking, cancellations) are rejected by the guard.

The guard uses multicall(bytes[]) to batch multiple performCall invocations into a single EVM transaction, enabling atomic-looking deposit and withdrawal flows on the EVM side (even though HyperCore execution remains asynchronous).

See also